Makefile Tips and Tricks - GNU Make

http://www.gnu.org/software/make/manual/make.html


Index of Concepts

append '-' before command to ignore error in makefile and
--silent with make or '@' before every command to echo off
eg:
  -rm foo
  -include Makefile_vars inc.mk
  @echo " Only once printed ";

Implicit variables
MAKELEVEL - Gives level of the make recursive subdir entries


Appendix A Quick Reference



Function Call Syntax
A function call resembles a variable reference.
It looks like this:
$(function arguments)
or like this:
${function arguments}


Functions for Transforming Text

1.Test Functions for String Substitution and Analysis
$(subst from,to,text)
$(patsubst pattern,replacement,text)
$(strip string)
.........and so on
example : override CFLAGS += $(patsubst %,-I%,$(subst :, ,$(VPATH)))

2. So on.. Please click link for further details


.PHONY Target

Automatic Variables
$< $@ $? $*


Defining and Redefining Pattern Rules
Here are some examples of pattern rules actually predefined in make. First, the rule that compiles `.c' files into `.o' files:

%.o : %.c
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

defines a rule that can make any file x.o from x.c. The command uses the automatic variables `$@' and `$<' to substitute the names of the target file and the source file in each case where the rule applies (see Automatic Variables).