Makefile Options

http://www.hsrl.rutgers.edu/ug/make_help.html

dependecy1: dependencyA dependencyB ... dependencyN
[tab] command for dependency1

That is probably one of the simplest makefiles that could be made. When you type make, it automatically knows you want to compile the 'myprogram' dependency (because it is the first dependency it found in the makefile). It then looks at mainprog.cc and sees when the last time you changed it, if it has been updated since last you typed 'make' then it will run the 'gcc mainprog.cc ..." line. If not, then it will look at myclass.cc, if it has been edited then it will execute the 'gcc mainprog.cc ..." line, otherwise it will not do anything for this rule.

Before issuing any command in a target rule set there are certain special macros predefined.

1. $@ is the name of the file to be made.
2. $? is the names of the changed dependents.

So, for example, we could use a rule

printenv: printenv.c
[tab] $(CC) $(CFLAGS) $? $(LDFLAGS) -o $@

alternatively:

printenv: printenv.c
[tab] $(CC) $(CFLAGS) $@.c $(LDFLAGS) -o $@

There are two more special macros used in implicit rules. They are:

3. $< the name of the related file that caused the action.
4. $* the prefix shared by target and dependent files.

Example Target Rules
INC=../misc
OTHERS=../misc/lib.a

$(OTHERS):
[tab] cd $(INC); make lib.a

Beware:, the following will not work (but you'd think it should)

INC=../misc
OTHERS=../misc/lib.a

$(OTHERS):
[tab] cd $(INC)
[tab] make lib.a

Each command in the target rule is executed in a separate shell. This makes for some interesting constructs and long continuation lines.