Makefile Tips and Tricks - GNU Make

http://www.gnu.org/software/make/manual/make.html


Index of Concepts

append '-' before command to ignore error in makefile and
--silent with make or '@' before every command to echo off
eg:
  -rm foo
  -include Makefile_vars inc.mk
  @echo " Only once printed ";

Implicit variables
MAKELEVEL - Gives level of the make recursive subdir entries


Appendix A Quick Reference



Function Call Syntax
A function call resembles a variable reference.
It looks like this:
$(function arguments)
or like this:
${function arguments}


Functions for Transforming Text

1.Test Functions for String Substitution and Analysis
$(subst from,to,text)
$(patsubst pattern,replacement,text)
$(strip string)
.........and so on
example : override CFLAGS += $(patsubst %,-I%,$(subst :, ,$(VPATH)))

2. So on.. Please click link for further details


.PHONY Target

Automatic Variables
$< $@ $? $*


Defining and Redefining Pattern Rules
Here are some examples of pattern rules actually predefined in make. First, the rule that compiles `.c' files into `.o' files:

%.o : %.c
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

defines a rule that can make any file x.o from x.c. The command uses the automatic variables `$@' and `$<' to substitute the names of the target file and the source file in each case where the rule applies (see Automatic Variables).

Bash Script Tips

http://www.hsrl.rutgers.edu/ug/shell_help.html

Command line arguments to shell scripts are positional variables:
$0, $1, ... - The command and arguments.
   With $0 the command and the rest the arguments.

$# - The number of arguments.
$*, $@ - All the arguments as a blank separated string.
  Watch out for "$*" vs. "$@".
  And, some commands: shift

$$ - Current process id.
$? - The exit status of the last command. and return result of last function

Conditional Reference
${variable-word} - If the variable has been set, use it's value, else use word.

POSTSCRIPT=first;
echo POSTSCRIPT
POSTSCRIPT=${POSTSCRIPT-second};
export POSTSCRIPT
echo POSTSCRIPT

${variable:-word} - If the variable has been set and is not null, use it's value, else use word.

These are useful constructions for honoring the user environment.
Ie. the user of the script can override variable assignments. Cf. programs like lpr(1) honor the PRINTER environment variable, you can do the same trick with your shell scripts.

${variable:?word} -If variable is set use it's value, else print out word and exit. Useful for bailing out.

String concatenation
The braces are required for concatenation constructs.
$p_01 - The value of the variable "p_01".
${p}_01 - The value of the variable "p" with "_01" pasted onto the end.

Include configuration
. command

This runs the shell script from within the current shell script. For example:
# Read in configuration information
. /etc/hostconfig

Debugging
The shell has a number of flags that make debugging easier:
sh -n command -

Read the shell script but don't execute the commands. IE. check syntax.
sh -x command
Display commands and arguments as they're executed. In a lot of my shell scripts you'll see
# Uncomment the next line for testing
# set -x

Makefile Options

http://www.hsrl.rutgers.edu/ug/make_help.html

dependecy1: dependencyA dependencyB ... dependencyN
[tab] command for dependency1

That is probably one of the simplest makefiles that could be made. When you type make, it automatically knows you want to compile the 'myprogram' dependency (because it is the first dependency it found in the makefile). It then looks at mainprog.cc and sees when the last time you changed it, if it has been updated since last you typed 'make' then it will run the 'gcc mainprog.cc ..." line. If not, then it will look at myclass.cc, if it has been edited then it will execute the 'gcc mainprog.cc ..." line, otherwise it will not do anything for this rule.

Before issuing any command in a target rule set there are certain special macros predefined.

1. $@ is the name of the file to be made.
2. $? is the names of the changed dependents.

So, for example, we could use a rule

printenv: printenv.c
[tab] $(CC) $(CFLAGS) $? $(LDFLAGS) -o $@

alternatively:

printenv: printenv.c
[tab] $(CC) $(CFLAGS) $@.c $(LDFLAGS) -o $@

There are two more special macros used in implicit rules. They are:

3. $< the name of the related file that caused the action.
4. $* the prefix shared by target and dependent files.

Example Target Rules
INC=../misc
OTHERS=../misc/lib.a

$(OTHERS):
[tab] cd $(INC); make lib.a

Beware:, the following will not work (but you'd think it should)

INC=../misc
OTHERS=../misc/lib.a

$(OTHERS):
[tab] cd $(INC)
[tab] make lib.a

Each command in the target rule is executed in a separate shell. This makes for some interesting constructs and long continuation lines.

GCC Options and GDB notes

gcc example.c [options]

-S - Compiles and stops. Output is assembler code (suffix .S).
-o [name] - Gives executable as 'name'.
-E - Preprocess source file only.
    Comments will be discared unless -C is also specified.
    Creates #line directives unless -P is also specified.
-M - The preprocessor outputs one make rule containing the object file name for that source file, a colon, and the names of all the included files,including those coming from -include or -imacros command line options.
-W - Print extra warning messages.
    -Wall print all warnings


Example:
cat > example.c << EOF
#include <stdio.h>
#include <string.h>

int main()
{
printf("Hello world");
}
EOF
#


GDB notes:

Compile C code with -g option and run 'gdb a.out'
In gdb prompt set the break point as 'break main' or any function.
To run 'run '
To watch the particular variable set 'watch ' and if the variable get modified then it will get notified
To see the local variables 'info local'
To proceed next line 'n or next'
list to display the source code