Quick Makefile


CC=gcc
S = file1.c file2.c

O = $(S:%.c=%.o)

exe: ${O}
     $(CC) ${LIBS} -o $<



# pull in dependency info for *existing* .o files
-include $(OBJS:.o=.d)


%.o: %.c 

 $(CC) ${INCLUDES} $(CFLAGS) -MMD -o $@ -c $<

 gcc -MM $(CFLAGS) $*.c > $*.d

.PHONY clean
clean:
     \rm -rf *.o exe

Note: Green highlighted stuff optional or use -MMD, are used to create dependencies

Another Example:
--------------------
ERR = $(error found an error!)
.PHONY: err

err: ; $(ERR)